Module title: Programmable Logic Design

SCQF level: 10:
SCQF credit value: 20.00
ECTS credit value: 10

Module code: ELE10105
Module leader: Luigi La Spada
School School of Engineering and the Built Environment
Subject area group: Electronics Electrical and Mathematics
Prerequisites

Module code: ELE09102 and MEC09110
Module title: Electronic Systems
Examples of equivalent learning: Electronic or Digital Systems equivalent to SCQF level 9.

2018/9, Trimester 2, Face-to-Face, Edinburgh Napier University
Occurrence: 001
Primary mode of delivery: Face-to-Face
Location of delivery: MERCHISTON
Partner: Edinburgh Napier University
Member of staff responsible for delivering module: David Binnie
Module Organiser:


Learning, Teaching and Assessment (LTA) Approach:
Learning & teaching methods including their alignment to LOs
The principles and knowledge base underlying learning outcomes 1 to 4 will be covered in lectures. However, much of the material covered by the learning outcomes 1 to 4 is of a practical nature and will be covered in laboratory based sessions. This will involve several mini-projects, in which the students will be developing and experimenting with programmable logic devices and systems.

Embedding of employability/ PDP/ scholarship skills
All aspects of the module are directly related to current technologies in the field of digital system design, development and implementation. The laboratory facilities are used by the students throughout the module and are built around industry standard computer aided design and development tools. These are currently in widespread use throughout the world and the practical skills developed in modules are of immediate benefit to a wide-range of employment situations. There is currently a world-wide shortage of these skills.

Research/ teaching linkages
This is a rapidly developing field of study in which the School of Engineering and Built Environment has strong research interests in areas covered by this module. It is therefore appropriate that examples and case studies will be drawn from current active areas of research. This is particularly so for areas such as image processing and embedded processors, where the latest developments occur so rapidly that standard text books do not cover them.

Internationalisation
Technical developments in this area are almost entirely conducted in the international arena.

Formative Assessment:
The University is currently undertaking work to improve the quality of information provided on methods of assessment and feedback. Please refer to the section on Learning and Teaching Approaches above for further information about this module’s learning, teaching and assessment practices, including formative and summative approaches.

Summative Assessment:
The learning outcomes 1 and 2 will be assessed by two laboratory based mini-projects.. These will be worth 20% and 30% of the overall mark. A final design, development, implementation and test project will cover learning outcomes 3 and 4 and will be worth 50% of the module marks.


Student Activity (Notional Equivalent Study Hours (NESH))
Mode of activityLearning & Teaching ActivityNESH (Study Hours)
Face To Face Lecture 12
Face To Face Practical classes and workshops 39
Independent Learning Guided independent study 149
Total Study Hours200
Expected Total Study Hours for Module200


Assessment
Type of Assessment Weighting % LOs covered Week due Length in Hours/Words
Practical Skills Assessment 20 1, 2 4 HOURS= 2, WORDS= 0
Practical Skills Assessment 30 1,3 9 HOURS= 3, WORDS= 0
Report 50 3,4 14/15 HOURS= 15, WORDS= 0
Component 1 subtotal: 100
Component 2 subtotal: 0
Module subtotal: 100

Description of module content:

Introduction to the synthesis of combinational and sequential digital logic circuits.
VHDL: introduction; concurrent VHDL; sequential VHDL; libraries, packages and subroutines; structural VHDL; RAM and ROM; state machines; RTL synthesis.
The use of Modelsim in behavoural and timing verification, and optimisation; RTL design methodology.
FPGA Hardware: design flow; design entry; simulation;:; PLD technologies: static RAM, EPROM, fuse and anti-fuse; FPGA architectures; logic modules and cells, FPGA routing,; IO blocks and interfacing; FPGA types, key; Development boards, FPGA test benches and fault finding. FPGA Applications.

Learning Outcomes for module:

On completion of this module you will be able to:
LO1 acquire in-depth knowledge and practical experience of VHDL hardware programming
language: syntax and structures;
LO2 design,synthesise and optimise digital logic circuits in an ECAD environment
LO3 optimise and find faults in applied digital logic circuits;
LO4 implement and test a programmed FPGA.

Indicative References and Reading List - URL:

Please contact your Module Leader for details
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